BFR/Clean_5_24V_I/dbandHi = 0.0
BFR/Clean_5_24V_I/dbandLo = 0.0
BFR/Clean_5_24V_I/limitHi = 1000.0
BFR/Clean_5_24V_I/limitLo = 0.0
BFR/Dirty_24V_I/dbandHi = 0.0
BFR/Dirty_24V_I/dbandLo = 0.0
BFR/Dirty_24V_I/limitHi = 1000.0
BFR/Dirty_24V_I/limitLo = 0.0
BFR/Dirty_28V_I/dbandHi = 0.0
BFR/Dirty_28V_I/dbandLo = 0.0
BFR/Dirty_28V_I/limitHi = 1000.0
BFR/Dirty_28V_I/limitLo = 0.0
BFR/Dirty_48V_I/dbandHi = 0.0
BFR/Dirty_48V_I/dbandLo = 0.0
BFR/Dirty_48V_I/limitHi = 1000.0
BFR/Dirty_48V_I/limitLo = 0.0
BFR/Heater_I/dbandHi = 0.0
BFR/Heater_I/dbandLo = 0.0
BFR/Heater_I/limitHi = 1000.0
BFR/Heater_I/limitLo = 0.0
BFR/Protection_I/dbandHi = 0.0
BFR/Protection_I/dbandLo = 0.0
BFR/Protection_I/limitHi = 1000.0
BFR/Protection_I/limitLo = 0.0
BFR/RebPs_0/dbandHi = 0.0
BFR/RebPs_0/dbandLo = 0.0
BFR/RebPs_0/limitHi = 1000.0
BFR/RebPs_0/limitLo = 0.0
BFR/SENSOR_PWS_17_I/dbandHi = 0.0
BFR/SENSOR_PWS_17_I/dbandLo = 0.0
BFR/SENSOR_PWS_17_I/limitHi = 0.0
BFR/SENSOR_PWS_17_I/limitLo = 0.0
PDU_24VC/Board_T/dbandHi = 2.0
PDU_24VC/Board_T/dbandLo = 0.0
PDU_24VC/Board_T/limitHi = 45.0
PDU_24VC/Board_T/limitLo = 0.0
PDU_24VC/Body_Purge_I/dbandHi = 0.0
PDU_24VC/Body_Purge_I/dbandLo = 0.0
PDU_24VC/Body_Purge_I/limitHi = 1000.0
PDU_24VC/Body_Purge_I/limitLo = 0.0
PDU_24VC/Body_Purge_V/dbandHi = 0.0
PDU_24VC/Body_Purge_V/dbandLo = 0.0
PDU_24VC/Body_Purge_V/limitHi = 0.0
PDU_24VC/Body_Purge_V/limitLo = 0.0
PDU_24VC/Bpu_Maq20_I/dbandHi = 0.0
PDU_24VC/Bpu_Maq20_I/dbandLo = 0.0
PDU_24VC/Bpu_Maq20_I/limitHi = 500.0
PDU_24VC/Bpu_Maq20_I/limitLo = 0.0
PDU_24VC/Bpu_Maq20_V/dbandHi = 0.0
PDU_24VC/Bpu_Maq20_V/dbandLo = 2.0
PDU_24VC/Bpu_Maq20_V/limitHi = 28.5
PDU_24VC/Bpu_Maq20_V/limitLo = 22.0
PDU_24VC/FPGA_T/dbandHi = 0.0
PDU_24VC/FPGA_T/dbandLo = 0.0
PDU_24VC/FPGA_T/limitHi = 50.0
PDU_24VC/FPGA_T/limitLo = 0.0
PDU_24VC/Fes_Shu_HCU_I/dbandHi = 0.0
PDU_24VC/Fes_Shu_HCU_I/dbandLo = 0.0
PDU_24VC/Fes_Shu_HCU_I/limitHi = 1000.0
PDU_24VC/Fes_Shu_HCU_I/limitLo = 0.0
PDU_24VC/Fes_Shu_HCU_V/dbandHi = 0.0
PDU_24VC/Fes_Shu_HCU_V/dbandLo = 2.0
PDU_24VC/Fes_Shu_HCU_V/limitHi = 28.5
PDU_24VC/Fes_Shu_HCU_V/limitLo = 22.0
PDU_24VC/Gauges_I/dbandHi = 0.0
PDU_24VC/Gauges_I/dbandLo = 0.0
PDU_24VC/Gauges_I/limitHi = 500.0
PDU_24VC/Gauges_I/limitLo = 0.0
PDU_24VC/Gauges_V/dbandHi = 0.0
PDU_24VC/Gauges_V/dbandLo = 2.0
PDU_24VC/Gauges_V/limitHi = 28.5
PDU_24VC/Gauges_V/limitLo = 22.0
PDU_24VC/Ion_Pumps_I/dbandHi = 0.0
PDU_24VC/Ion_Pumps_I/dbandLo = 0.0
PDU_24VC/Ion_Pumps_I/limitHi = 1500.0
PDU_24VC/Ion_Pumps_I/limitLo = 0.0
PDU_24VC/Ion_Pumps_V/dbandHi = 0.0
PDU_24VC/Ion_Pumps_V/dbandLo = 2.0
PDU_24VC/Ion_Pumps_V/limitHi = 28.5
PDU_24VC/Ion_Pumps_V/limitLo = 22.0
PDU_24VC/J8_I/dbandHi = 0.0
PDU_24VC/J8_I/dbandLo = 0.0
PDU_24VC/J8_I/limitHi = 0.0
PDU_24VC/J8_I/limitLo = 0.0
PDU_24VC/J8_V/dbandHi = 0.0
PDU_24VC/J8_V/dbandLo = 0.0
PDU_24VC/J8_V/limitHi = 0.0
PDU_24VC/J8_V/limitLo = 0.0
PDU_24VC/J11_I/dbandHi = 0.0
PDU_24VC/J11_I/dbandLo = 0.0
PDU_24VC/J11_I/limitHi = 0.0
PDU_24VC/J11_I/limitLo = 0.0
PDU_24VC/J11_V/dbandHi = 0.0
PDU_24VC/J11_V/dbandLo = 0.0
PDU_24VC/J11_V/limitHi = 0.0
PDU_24VC/J11_V/limitLo = 0.0
PDU_24VC/J12_I/dbandHi = 0.0
PDU_24VC/J12_I/dbandLo = 0.0
PDU_24VC/J12_I/limitHi = 0.0
PDU_24VC/J12_I/limitLo = 0.0
PDU_24VC/J12_V/dbandHi = 0.0
PDU_24VC/J12_V/dbandLo = 0.0
PDU_24VC/J12_V/limitHi = 0.0
PDU_24VC/J12_V/limitLo = 0.0
PDU_24VC/J6_I/dbandHi = 0.0
PDU_24VC/J6_I/dbandLo = 0.0
PDU_24VC/J6_I/limitHi = 0.0
PDU_24VC/J6_I/limitLo = 0.0
PDU_24VC/J6_V/dbandHi = 0.0
PDU_24VC/J6_V/dbandLo = 0.0
PDU_24VC/J6_V/limitHi = 0.0
PDU_24VC/J6_V/limitLo = 0.0
PDU_24VC/J7_I/dbandHi = 0.0
PDU_24VC/J7_I/dbandLo = 0.0
PDU_24VC/J7_I/limitHi = 0.0
PDU_24VC/J7_I/limitLo = 0.0
PDU_24VC/J7_V/dbandHi = 0.0
PDU_24VC/J7_V/dbandLo = 0.0
PDU_24VC/J7_V/limitHi = 0.0
PDU_24VC/J7_V/limitLo = 0.0
PDU_24VC/J9_I/dbandHi = 0.0
PDU_24VC/J9_I/dbandLo = 0.0
PDU_24VC/J9_I/limitHi = 0.0
PDU_24VC/J9_I/limitLo = 0.0
PDU_24VC/J9_V/dbandHi = 0.0
PDU_24VC/J9_V/dbandLo = 0.0
PDU_24VC/J9_V/limitHi = 0.0
PDU_24VC/J9_V/limitLo = 0.0
PDU_24VC/Main_I/dbandHi = 0.0
PDU_24VC/Main_I/dbandLo = 0.0
PDU_24VC/Main_I/limitHi = 2000.0
PDU_24VC/Main_I/limitLo = 0.0
PDU_24VC/Main_T/dbandHi = 2.0
PDU_24VC/Main_T/dbandLo = 0.0
PDU_24VC/Main_T/limitHi = 45.0
PDU_24VC/Main_T/limitLo = 0.0
PDU_24VC/Main_V/dbandHi = 0.0
PDU_24VC/Main_V/dbandLo = 2.0
PDU_24VC/Main_V/limitHi = 28.5
PDU_24VC/Main_V/limitLo = 22.0
PDU_24VC/Pwr_Cry_HCU_I/dbandHi = 0.0
PDU_24VC/Pwr_Cry_HCU_I/dbandLo = 0.0
PDU_24VC/Pwr_Cry_HCU_I/limitHi = 1000.0
PDU_24VC/Pwr_Cry_HCU_I/limitLo = 0.0
PDU_24VC/Pwr_Cry_HCU_V/dbandHi = 0.0
PDU_24VC/Pwr_Cry_HCU_V/dbandLo = 2.0
PDU_24VC/Pwr_Cry_HCU_V/limitHi = 28.5
PDU_24VC/Pwr_Cry_HCU_V/limitLo = 22.0
PDU_24VD/Board_T/dbandHi = 2.0
PDU_24VD/Board_T/dbandLo = 0.0
PDU_24VD/Board_T/limitHi = 45.0
PDU_24VD/Board_T/limitLo = 0.0
PDU_24VD/FES_I/dbandHi = 0.0
PDU_24VD/FES_I/dbandLo = 0.0
PDU_24VD/FES_I/limitHi = 0.0
PDU_24VD/FES_I/limitLo = 0.0
PDU_24VD/FES_V/dbandHi = 0.0
PDU_24VD/FES_V/dbandLo = 0.0
PDU_24VD/FES_V/limitHi = 0.0
PDU_24VD/FES_V/limitLo = 0.0
PDU_24VD/FPGA_T/dbandHi = 0.0
PDU_24VD/FPGA_T/dbandLo = 0.0
PDU_24VD/FPGA_T/limitHi = 50.0
PDU_24VD/FPGA_T/limitLo = 0.0
PDU_24VD/Main_I/dbandHi = 0.0
PDU_24VD/Main_I/dbandLo = 0.0
PDU_24VD/Main_I/limitHi = 2000.0
PDU_24VD/Main_I/limitLo = 0.0
PDU_24VD/Main_T/dbandHi = 2.0
PDU_24VD/Main_T/dbandLo = 0.0
PDU_24VD/Main_T/limitHi = 45.0
PDU_24VD/Main_T/limitLo = 0.0
PDU_24VD/Main_V/dbandHi = 0.0
PDU_24VD/Main_V/dbandLo = 2.0
PDU_24VD/Main_V/limitHi = 24.5
PDU_24VD/Main_V/limitLo = 20.0
PDU_48V/Board_T/dbandHi = 2.0
PDU_48V/Board_T/dbandLo = 0.0
PDU_48V/Board_T/limitHi = 45.0
PDU_48V/Board_T/limitLo = 0.0
PDU_48V/CryoTel0_I/dbandHi = 0.0
PDU_48V/CryoTel0_I/dbandLo = 0.0
PDU_48V/CryoTel0_I/limitHi = 0.0
PDU_48V/CryoTel0_I/limitLo = 0.0
PDU_48V/CryoTel0_V/dbandHi = 0.0
PDU_48V/CryoTel0_V/dbandLo = 0.0
PDU_48V/CryoTel0_V/limitHi = 0.0
PDU_48V/CryoTel0_V/limitLo = 0.0
PDU_48V/CryoTel1_I/dbandHi = 0.0
PDU_48V/CryoTel1_I/dbandLo = 0.0
PDU_48V/CryoTel1_I/limitHi = 0.0
PDU_48V/CryoTel1_I/limitLo = 0.0
PDU_48V/CryoTel1_V/dbandHi = 0.0
PDU_48V/CryoTel1_V/dbandLo = 0.0
PDU_48V/CryoTel1_V/limitHi = 0.0
PDU_48V/CryoTel1_V/limitLo = 0.0
PDU_48V/CryoTel2_I/dbandHi = 0.0
PDU_48V/CryoTel2_I/dbandLo = 0.0
PDU_48V/CryoTel2_I/limitHi = 0.0
PDU_48V/CryoTel2_I/limitLo = 0.0
PDU_48V/CryoTel2_V/dbandHi = 0.0
PDU_48V/CryoTel2_V/dbandLo = 0.0
PDU_48V/CryoTel2_V/limitHi = 0.0
PDU_48V/CryoTel2_V/limitLo = 0.0
PDU_48V/FPGA_T/dbandHi = 0.0
PDU_48V/FPGA_T/dbandLo = 0.0
PDU_48V/FPGA_T/limitHi = 50.0
PDU_48V/FPGA_T/limitLo = 0.0
PDU_48V/Main_I/dbandHi = 0.0
PDU_48V/Main_I/dbandLo = 0.0
PDU_48V/Main_I/limitHi = 2000.0
PDU_48V/Main_I/limitLo = 0.0
PDU_48V/Main_T/dbandHi = 2.0
PDU_48V/Main_T/dbandLo = 0.0
PDU_48V/Main_T/limitHi = 45.0
PDU_48V/Main_T/limitLo = 0.0
PDU_48V/Main_V/dbandHi = 0.0
PDU_48V/Main_V/dbandLo = 2.0
PDU_48V/Main_V/limitHi = 49.0
PDU_48V/Main_V/limitLo = 44.0
PDU_48V/REB_BULK_I/dbandHi = 0.0
PDU_48V/REB_BULK_I/dbandLo = 0.0
PDU_48V/REB_BULK_I/limitHi = 0.0
PDU_48V/REB_BULK_I/limitLo = 0.0
PDU_48V/REB_BULK_V/dbandHi = 0.0
PDU_48V/REB_BULK_V/dbandLo = 0.0
PDU_48V/REB_BULK_V/limitHi = 0.0
PDU_48V/REB_BULK_V/limitLo = 0.0
PDU_5V/OTM_3_A_I/dbandHi = 0.0
PDU_5V/OTM_3_A_I/dbandLo = 0.0
PDU_5V/OTM_3_A_I/limitHi = 1000.0
PDU_5V/OTM_3_A_I/limitLo = 0.0
PDU_5V/OTM_3_A_V/dbandHi = 0.0
PDU_5V/OTM_3_A_V/dbandLo = 0.0
PDU_5V/OTM_3_A_V/limitHi = 5.5
PDU_5V/OTM_3_A_V/limitLo = 4.7
PDU_5V/OTM_3_B_I/dbandHi = 0.0
PDU_5V/OTM_3_B_I/dbandLo = 0.0
PDU_5V/OTM_3_B_I/limitHi = 1000.0
PDU_5V/OTM_3_B_I/limitLo = 0.0
PDU_5V/OTM_3_B_V/dbandHi = 0.0
PDU_5V/OTM_3_B_V/dbandLo = 0.0
PDU_5V/OTM_3_B_V/limitHi = 5.5
PDU_5V/OTM_3_B_V/limitLo = 4.7
